Complimentary metal oxide semiconductor (CMOS) structures are the core active elements of modern electronics. Undoubtedly, the major material enabling features of Si CMOS are the superb quality of the native silicon dioxide (SiO2), Si/SiO2 interface and high crystalline perfection of the Si substrates. The field effect transistor (FET) implemented as CMOS is scalable. That is, speed and complexity improves with decreasing device feature sizes. This concept makes CMOS architecture a powerful methodology. Deep submicron room-temperature bulk Si CMOS is presently the main technology used for ultra large scale integrated circuits (ULSICs).
Because silicon is the major semiconductor material used in the semiconductor industry, silicon dioxide (SiO2) is the major insulating material used in the gate insulating layer. Silicon dioxide is a natural material that can be easily grown thermally through a steam process. Also, the silicon dioxide forms a bond with the crystalline silicon active layer that determines most of the characteristics of the FET so that it is very difficult to change the insulating material of the gate insulating layer without having deleterious effects on the FET.
However, several problems do arise from the use of silicon dioxide as the gate insulating layer. Continued scaling of current CMOS architecture is reaching the limits of the material properties of both the SiO2 gate dielectric and bulk Si substrate. As the length and thickness of the gate insulating layer is made smaller, defects and other materials in the gate insulating layer greatly affect the reliability, lifetime, and operating characteristics of the FET. For example, any impurities in the gate stack, such as the dopant material used in doping of layers of the gate stack, can cause serious problems. The impurities or doping materials are a problem because they migrate into the gate insulating layer and sometimes even into the active layer to produce defects and changes in operating characteristics.
One potential solution to the scaling of field effect transistors is the use of a second, buried gate below the active channel. It has been shown that the double gate structure reduces short channel effects and parasitic capacitance in field effect transistors so that they can be scaled further (i.e. thinner and shorter channels) than bulk-Si. In general, however, prior art suggestions for fabricating double gate FETs are extremely complicated, expensive, and very difficult to implement. Some of the prior art suggestions include forming the double gate FET in a vertical orientation with the gates on either side of a channel and the source and drain at the ends. This structure is extremely difficult to integrate into present semiconductor manufacturing techniques. Another structure is formed by removing material above and below the channel leaving a bridge structure and then filling the voids with electrically conductive gate material. This method is extremely complicated and difficult to consistently produce workable devices with constant characteristics.
Clearly, one of the major problems that arises in prior art attempts to fabricate planar double gate FETs is the buried conductive layer that ultimately forms the lower gate. In the semiconductor industry, forming a good conducting layer below, for example, crystalline or single crystal silicon is virtually unknown. One of the most common conductive buried layers includes heavily doped silicon areas, which is undesirable because free doping material has a tendency to migrate and corrupt other components, thereby shortening the life of the device and changing various characteristics (e.g. the threshold voltage). Also, heavily doped areas do not have good conductivity, thereby producing poor gate material.
An additional problem that arises in prior art planar structures is alignment of the upper and lower gates. It is well known that misaligned gates cause serious degradation in the performance of the device. In the prior art some attempts to minimize misalignment effects include oversized bottom gates and minimum sized bottom gates. In each case the results are poorer than properly aligned upper and lower gates.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved method of fabricating double gate field effect transistors and the new and improved double gate structure field effect transistors.
Another object of the invention is to provide a new and improved method of fabricating double gate structure field effect transistors to improve manufacturing consistency, to simplify the fabrication process, and to provide double gate field effect transistors with improved reliability, lifetime, and operating characteristics.
A further object of the present invention is to provide a new and improved buried conductive layer and fabrication process for use in field effect transistors that can be easily integrated into present day semiconductor manufacturing processes.